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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 0.6 / oct. 2004 1 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash document title 512mbit (64mx8bit / 32mx16 bit) nand flash memory revision history no. history draft date remark 0.0 initial draft sep.17.2003 preliminary 0.1 renewal product group oct.07.2003 preliminary 0.2 make a decision of pkg information nov.08.2003 preliminary 0.3 append 1.8v operation product to data sheet dec.01.2003 preliminary 0.4 1) add errata 2) modify the description of device operations - /ce don?t care enabled(disabled) -> sequential row read disabled (enabled) (page22) 3) add the description of system interface using ce don?t care (page37) mar.28.2004 preliminary 0.5 1) delete errata 2) change characteristics (3v product) 3) delete cache program jun. 01. 2004 preliminary 0.6 1) change tsop1, wsop1, fbga package dimension 2) edit tsop1, wsop1 package figures 3) change fbga package figure oct. 20. 2004 tcry trea@id read before 60 + tr 35 after 70 + tr 45 twc twh twp trc treh trp trea@id read specification 50 15 25 50 15 30 35 relaxed value60 2040602040 45
this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 0.6 / oct. 2004 2 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 or x16 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27usxx121m - 1.8v device: vcc = 1.7 to 1.95v : hy27ssxx121m memory cell array - 528mbit = 528 bytes x 32 pages x 4,096 blocks page size - x8 device : (512 + 16 spare) bytes : hy27(u/s)s08121m - x16 device: (256 + 8 spare) words : hy27(u/s)s16121m block size - x8 device: (16k + 512 spare) bytes - x16 device: (8k + 256 spare) words page read / program - random access: 12us (max) - sequential access: 50ns (min) - page program time: 200us (typ) copy back program mode - fast page copy without external buffering fast block erase - block erase time: 2ms (typ) status register electronic signature sequential row read option automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles - 10 years data retention package - hy27us(08/16)121m-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27us(08/16) 121m-t (lead) - hy27us(08/16)121m-tp (lead free) - hy27us08121m-v(p) : 48-pin wsop1 (12 x 17 x 0.7 mm) - hy27us08121m-v (lead) - hy27us08121m-vp (lead free) - hy27(u/s)s(08/16)121m-f(p) : 63-ball fbga (8.5 x 15 x 1.2 mm) - hy27us(08/16) 121m-f (lead) - hy27us(08/16)121m-fp (lead free) - hy27ss(08/16)121m-f (lead) - hy27ss(08/16)121m-fp (lead free)
rev 0.6 / oct. 2004 3 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash description the hynix hy27(u/s)sxx121m series is a family of non-vola tile flash memories that use nand cell technology. the devices operate 3.3v and 1.8v voltage supply. the size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. the address lines are multiplexed with th e data input/ output signals on a multiplexed x8 or x16 input/ output bus. this interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. each block can be programmed and erased over 100,000 cycles. to extend the lifetime of nand flash devices it is strongly recommended to implement an error correction code (ecc). a write protect pin is available to give a hard- ware protection against program and erase operations. the devices feature an open-drain ready/busy output that ca n be used to identify if the program/ erase/read (per) controller is currently active. the use of an open-drain outp ut allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a copy back command is available to optimize the management of defective blocks. when a page program operation fails, the data can be programmed in another page wi thout having to resend th e data to be programmed. the devices are available in the following packages: - 48-tsop1 (12 x 20 x 1.2 mm) - 48-wsop1 (12 x 17 x 0.7 mm) - 63-fbga (8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch) three options are available for the nand flash family: - automatic page 0 read after power-up, which allows the microcontroller to directly do wnload the boot code from page 0. - chip enable dont care, which allows code to be directly downloaded by a microcontroller, as chip enable transitions during the latency time do not stop the read operation. - a serial number, which allows each device to be uniquely identified. the serial number options is subject to an nda (non disclosure agreement) and so not described in the datasheet. for more deta ils of this option contact your near- est hynix sales office. devices are shipped from the factory with block 0 always vali d and the memory content bits, in valid blocks, erased to '1'.
rev 0.6 / oct. 2004 4 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash i/o 8-15 data input/outputs for x16 device i/o 0-7 data input/output, a ddress inputs, or com- mand inputs for x8 and x16 device ale address latch enable cle command latch enable ce chip enable re read enable rb read/busy (open-drain output) we write enable wp write protect vcc supply voltage vss ground nc not connected internally du do not use table 1: signal name figure 1: logic diagram figure 2. logic block diagram nand flash vcc vss ale cle ce re we wp i/o8-i/o15, x16 i/o0-i/o7, x8/x16 rb i/o buffers & latches page buffer cache register y decoder nand flash memory array address register/counter command interface logic command register p/e/r controller, high voltage generator x decoder ale cle we ce wp re i/o0-i/o7, x8/x16 i/o8-i/o15, x16 rb
rev 0.6 / oct. 2004 5 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash 1 12 13 24 48 37 36 25 nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc vcc vss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc nc nc nc nc nc nc ce nc nc vcc vss nc nc cle ale nc nc nc nc nc rb re we wp nand flash (x8) 1 12 13 24 48 37 36 25 vss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 nc nc vcc nc nc nc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 vss nc nc nc nc nc nc ce nc nc vcc vss nc nc cle ale nc nc nc nc nc rb re we wp nand flash (x16) 1 12 13 24 48 37 36 25 nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc vcc vss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc nc nc nc nc nc nc ce nc nc vcc vss nc nc cle ale nc nc nc nc nc rb re we wp nand flash (x8) 1 12 13 24 48 37 36 25 nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc vcc vss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc nc nc nc nc nc nc ce nc nc vcc vss nc nc cle ale nc nc nc nc nc rb rb re re we we wp wp nand flash (x8) 1 12 13 24 48 37 36 25 vss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 nc nc vcc nc nc nc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 vss nc nc nc nc nc nc ce nc nc vcc vss nc nc cle ale nc nc nc nc nc rb re we wp nand flash (x16) 1 12 13 24 48 37 36 25 vss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 nc nc vcc nc nc nc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 vss nc nc nc nc nc nc ce nc nc vcc vss nc nc cle ale nc nc nc nc nc rb rb re re we we wp wp nand flash (x16) figure 3. 48-tsop1 contactions, x8 and x16 device figure 4. 48-wsop1 contactions, x8 device 12 13 24 nand flash wsop1 (x8) 37 36 25 nc nc du nc i/o7 i/o6 i/o5 i/o4 nc du nc vcc vss nc du nc i/o3 i/o2 i/o1 i/o0 nc du nc nc nc nc du nc nc nc rb re ce du nc vcc vss nc du cle ale we wp nc nc du nc nc 1 48 12 13 24 nand flash wsop1 (x8) 37 36 25 nc nc du nc i/o7 i/o6 i/o5 i/o4 nc du nc vcc vss nc du nc i/o3 i/o2 i/o1 i/o0 nc du nc nc nc nc du nc nc nc rb re ce du nc vcc vss nc du cle ale we wp nc nc du nc nc 1 48
rev 0.6 / oct. 2004 6 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 5. 63-fbga contactions, x8 device (top view through package) figure 6. 63-fbga contactions, x16 device (top view through package) 6 5 4 3 2 1 a b c d e f g h ale vss ce we rb nc re cle nc nc nc nc nc nc nc nc nc wp nc nc nc nc nc nc nc nc nc nc nc nc nc i/o0 nc nc nc vcc nc i/o1 nc vcc i/o5 i/o7 vss i/o2 i/o3 i/o4 i/o6 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10 9 8 7 j k l m 4 6 5 4 3 2 1 a b c d e f g h ale vss ce we rb nc re cle nc nc nc nc nc nc nc nc nc wp nc nc nc nc nc nc nc nc nc i/o5 nc i/o1 vcc vcc i/o6 i/o15 vss i/o2 i/o11 i/o4 i/o13 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10 9 8 7 j k l m 4 i/o7 i/o8 i/o10 i/o12 i/o14 i/o0 i/o9 i/o3
rev 0.6 / oct. 2004 7 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash memory array organization the memory array is made up of nand structures where 16 cells are connected in series. the memory array is organized in blocks where each block contains 32 pages. th e array is split into two areas, the main area and the spare area. the main area of the array is used to store data whereas the spare area is typically used to store error correction codes, softwa re flags or bad block identification. in x8 devices the pages are split into a main area with two half pages of 256 bytes each and a spare area of 16 bytes. in the x16 devices the pages are split into a 256 word main area and an 8 word spare area. refer to figure 8, memory array organization. bad blocks the nand flash 528 byte/ 264 word page devices may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. additional bad blocks may develop during the lifetime of the device. the bad block information is written prior to shipping (r efer to bad block management section for more details). the values shown include both the bad blocks that are pres ent when the device is shi pped and the bad blocks that could develop later on. these blocks need to be managed using bad blocks ma nagement, block replacement or error correction codes. figure 7. memory array organization 1st half page (256 bytes) 2nd half page (256 bytes) block page 512 bytes 16 bytes 8 bits 8 bits 512 bytes 16 bytes page buffer, 528 bytes x8 devices block= 32 pages page= 528 bytes (512+16) main area block page 256 words 8 words 16 bits 16 bits 256 words 8 words page buffer, 264 words x16 devices block= 32 pages page= 264 words (256+8) s p a r e a r e a
rev 0.6 / oct. 2004 8 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash signal descriptions see figure 1, logic diagram and table 1, signal names, for a brief overview of the signals connecte d to this device. inputs/outputs (i/o 0 -i/o 7 ) input/outputs 0 to 7 are used to input the selected address, output the data during a re ad opertion or input a com- mand or data during a write operation. the inputs are latched on the rising edge of write enable. i/o 0 -i/o 7 can be left floating when the device is desele cted or the outputs are disabled. inputs/outputs (i/o 8 -i/o 15 ) input/outputs 8 to 15 are only available in x16 devices. they are used to output the data during a read operation or input data during a write operation. command and address inputs only require i/o 0 to i/o 7 . the inputs are latched on the rising edge of write enable. i/o 8 -i/o 15 can be left floating when the device is deselected or the outputs are disabled. address latch enable (ale) the address latch enable activates the latching of the addr ess inputs in the command in terface. when ale is high, the inputs are latched on the rising edge of write enable. command latch enable (cle) the command latch enable activates the latching of the command inputs in the command interface. when cle is high, the inputs are la tched on the rising edge of write enable. chip enable (ce ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip en- able is low, v il , the device is selected. if chip enable goes high, v ih , while the device is busy, the device remains se- lected and does not go into standby mode. when the device is executing a sequential row read operation, chip enable must be held low (from the second page read onwards) during the time that the device is busy (t blbh1 ). if chip enable goes high during t blbh1 the operation is aborted. read enable (re ) the read enable, re , controls the sequential data output during read operations. data is valid t rlqv after the falling edge of re . the falling edge of re also increments the internal column address counter by one. write enable (we ). the write enable input, we , controls writing to the command interface, input address and data latches. both addresses and data are latc hed on the rising edge of write enable. during power-up and power-down a recovery time of 1us (m in) is required before the command interface is ready to accept a command. it is recommended to keep write enable high during the recovery time. write protect (wp ). the write protect pin is an input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down.
rev 0.6 / oct. 2004 9 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash ready/busy (rb ) the ready/busy output, rb , is an open-drain output that can be used to identify if the program/ erase/ read (per) controller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes ready/busy goes high, v oh . the use of an open-drain output allows the ready/ busy pi ns from several memories to be connected to a single pull- up resistor. a low will then indicate that one, or more, of the memories is busy. refer to the ready/busy signal electrical characteristics sect ion for details on how to calc ulate the value of the pull-up resistor. v cc supply voltage v cc provides the power supply to the intern al core of the memory device. it is the main power supply for all operations (read,program and erase). an internal voltage detector di sables all functions whenever v cc is below 2.5v (for 3v devices) or 1.5v (for 1.8v devices) to protect the device from any invol untary program/erase duri ng power-transitions. each device in a system should have v cc decoupled with a 0.1uf capacitor. the pcb track widths should be sufficient to carry the required program and erase currents v ss ground ground, v ss , is the reference for the power supply. it must be connected to the system ground. bus operations there are six standard bus operations that control the memory. each of these is described in this section, see tables 2, bus operations, for a summary. command input command input bus operations are used to give commands to the memory. command are a ccepted when chip enable is low, command latch enable is high, address latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o 0 to i/o 7 are used to input commands. see figure 21 and table 14 for details of the timings requirements. address input address input bus operations are used to input the memory address. four bu s cycles are required to input the addresses for the 512mb devices (refer to tables 3 and 4, address insertion). the addre sses are accepted when chip enable is low, address latch enable is high, command latch enable is low and read enable is high. they are latched on the rising edge of the wr ite enable signal. only i/o 0 to i/o 7 are used to input addresses. see figure 22 and table 14 for details of the timings requirements. data input data input bus operations are used to input the data to be programmed. data is accepted only when chip enable is low, address latch enable is low, command latch enable is low and read enable is high. the data is latched on the rising edge of the write enable signal. the data is input sequentially using the write enable signal. see figure 23 and tables 14 and 15 for details of the timings requirements.
rev 0.6 / oct. 2004 10 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash data output data output bus operations are used to read: the data in the memory array, th e status register, the electronic signa- ture and the serial number. data is outp ut when chip enable is low, write en able is high, address latch enable is low, and command latch enable is low. the data is output sequentially using the read enable signal. see figure 24 and table 15 for details of the timings requirements. write protect write protect bus operations are used to protect the memo ry against program or erase operations. when the write protect signal is low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. the write protect sign al is not latched by write enable to ensure protection even during power-up. standby when chip enable is high the memory enters standby mode , the device is deselected, outputs are disabled and power consumption is reduced.
rev 0.6 / oct. 2004 11 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 2. bus operation note : (1) only for x16 devices. (2) wp must be v ih when issuing a prog ram or erase command. table 3: address insertion, x8 devices note: (1). a8 is set low or high by the 00h or 01h command, see pointer operations section. (2). any address input cycles will be ignored with tals > 0ns. table4: address insertion, x16 devices note: (1). a8 is don ' t care in x16 devices. (2). any address input cycles will be ignored with tals > 0ns. (3). a1 is the least significant address for x16 devices. (4). the 01h comma nd is not used in x16 devices. bus operation ce ale cle re we wp i/o 0 - i/o 7 i/o 8 - i/o 15 (1) command input v il v il v ih v ih rising x (2) command x address input v il v ih v il v ih rising x address x data input v il v il v il v ih rising x data input data input data output v il v il v il falling v ih x data output data output write protect xxxxxv il xx standby v ih xxxxx x x bus cycle i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 1st cycle a7 a6 a5 a4 a3 a2 a1 a0 2nd cycle a16 a15 a14 a13 a12 a11 a10 a9 3rd cycle a24 a23 a22 a21 a20 a19 a18 a17 4th cycle v il v il v il v il v il v il v il a25 bus cycle i/o 8 -i/ o 15 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 1st cycle x a7 a6 a5 a4a3a2a1a0 2nd cycle x a16 a15 a14 a13 a12 a11 a10 a9 3rd cycle x a24 a23 a22 a21 a20 a19 a18 a17 4th cycle v il v il v il v il v il v il v il v il a25
rev 0.6 / oct. 2004 12 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash command set all bus write operations to the device are interpreted by the command interface. the commands are input on i/o 0 -i/ o 7 and are latched on the rising edge of write enable when the command latch enable signal is high. device opera- tions are selected by writin g specific commands to the command register . the two-step command sequences for pro- gram and erase operations are imposed to maximize data security. the commands are summarized in table 5, commands. table 5: command set note: (1). any undefined command sequence will be ignored by the device. (2). bus write operation(1 st , 2 nd and 3 rd cycle) : the bus cycles are only shown for issuing the codes. the cycles required to input the addresses or input/output data are not shown. device operations pointer operations as the nand flash memories contain two different areas for x16 devices and three different areas for x8 devices (see figure 8) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they select the most significant column address). the read a and read b commands act as pointers to the ma in memory area. their use depends on the bus width of the device. - in x16 devices the read a command (00h) sets the pointer to area a (the whole of the main area) that is words 0 to 255. - in x8 devices the read a command (00h ) sets the pointer to area a (the first half of the main ar ea) that is bytes 0 to 255, and the read b command (01h) sets the pointer to area b (the second half of the main area) that is bytes 256 to 511. in both the x8 and x16 devices the read c command (50h), ac ts as a pointer to area c (the spare memory area) that is bytes 512 to 527 or words 256 to 263. once the read a and read c commands have been issued the pointer remains in the respective areas until another function 1st cycle 2nd cycle 3rd cycle command accepted during busy read a 00h - - read b 01h - - read c 50h - - read electrinic signature 90h - - read status register 70h - - yes page program 80h 10h - copy back program 00h 8ah 10h block erase 60h d0h - reset ffh - - yes
rev 0.6 / oct. 2004 13 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash pointer code is issued. howeve r, the read b command is effective for only one operation, once an operation has been executed in area b the pointer re turns automaticall y to area a. the pointer operations can also be used before a program op eration, that is the appropriate code (00h, 01h or 50h) can be issued before the program command 80h is issued (see figure 9). figure 8. pointer operation figure 9. pointer operations for programming area a (00h) area b (01h) area c (50h) bytes 0-255 bytes 256-511 bytes 512-527 a b c pointer (00h, 01h, 50h) x8 devices page buffer area c (50h) words 256-263 c x16 devices page buffer area a (00h) words 0-256 a pointer (00h, 50h) 10h 80h 01h address inputs 80h data input 10h address inputs 01h data input area b area b, c can be programmed depending on how much data is input. the 01h command must be re-issued before each program. 10h 80h 00h address inputs 80h data input 10h address inputs 00h data input area a area a, b, c can be programmed depending on how much data is input. subsequent 00h commands can be omitted. 10h 80h 50h address inputs 80h data input 10h address inputs 50h data input area c only areas c can be programmed. subsequent 50h commands can be omitted. i/o i/o i/o
rev 0.6 / oct. 2004 14 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash read memory array each operation to read the memory area starts with a poin ter operation as shown in the pointer operations section. the device defaults to read a mode after powerup or a rese t operation. devices, where page0 is read automatically at power-up, are available on request. when reading the spare area addresses: - a0 to a3 (x8 devices) - a0 to a2 (x16 devices) are used to set the start address of the spare area while addresses: - a4 to a7 (x8 devices) - a3 to a7 (x16 devices) are ignored. once the read a or read c commands have been issued they do not need to be reissued for subsequent read opera- tions as the pointer remains in the respective area. however, the read b co mmand is effective for only one operation, once an operation has been executed in area b the pointe r returns automatically to ar ea a and so another read b command is required to start another read operation in area b. once a read command is issued three types of operations are available: random read, page read and sequential row read. random read each time the command is issued the first read is random read. page read after the random read access the page data is tr ansferred to the page buffer in a time of t whbh (refer to table 15 for value). once the transfer is complete the ready/busy signal goes high. the data can then be read out sequentially (from selected column address to last column address) by pulsing th e read enable signal. sequential row read after the data in last column of the pa ge is output, if the read enable signal is pulsed and chip enable remains low then the next page is automatically lo aded into the page buffer and the read operation continues. a sequential row read operation can only be used to read within a block. if the block changes a new read command must be issued. refer to figures 12 and 13 for details of sequential row read operations. to terminate a sequential row read opera- tion set the chip enable sign al to high for more than t ehel . sequential row read is not available when the sequential row read option is disabled.
rev 0.6 / oct. 2004 15 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash note: 1. if t elwl is less than 10ns, t wlwh must be minimum 35ns, otherwise, t wlwh may be minimum 25ns. note: 1. highest address depends on device density. figure 10. read (a, b, c) operation figure 11. read block diagrams cle ale i/o rb tblbh1 (read) 00h/ 01h/ 50h command code address input data output (sequentially) busy ce we re area a (1st half page) area b (2nd half page) area c (spare) read a command, x8 devices a9-a25(1) a0-a7 area c (50h) read a command, x16 devices area a (main area) a9-a25(1) a0-a7 area a area c (spare) read c command, x8/x16 devices a9-a25(1) a0-a3 (x8) a0-a2 (x16) area a/b a4-a7 (x8), a3-a7 (x16) are don't care area a (1st half page) area c (spare) read b command, x8 devices a9-a25(1) a0-a7 area b (2nd half page)
rev 0.6 / oct. 2004 16 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 12. sequential row read operation area a (1 st half page) area b area c read a command, x8 devices (2 nd half page) (spare) block 1 st page 2 nd page n th page read b command, x8 devices area a (1 st half page) area b (2 nd half page) area c (spare) block 1 st page 2 nd page n th page area a area c (spare) read a command, x16 devices (main area) 1 st page 2 nd page n th page block area a area a/b area c (spare) read c command, x8/x16 devices 1 st page 2 nd page n th page block area a (1 st half page) area b area c read a command, x8 devices (2 nd half page) (spare) block 1 st page 2 nd page n th page area a (1 st half page) area a (1 st half page) area b area c read a command, x8 devices (2 nd half page) (spare) block 1 st page 2 nd page n th page block 1 st page 2 nd page n th page read b command, x8 devices area a (1 st half page) area b (2 nd half page) area c (spare) block 1 st page 2 nd page n th page read b command, x8 devices area a (1 st half page) area a (1 st half page) area b (2 nd half page) area c (spare) block 1 st page 2 nd page n th page block 1 st page 2 nd page n th page area a area c (spare) read a command, x16 devices (main area) 1 st page 2 nd page n th page block area a area c (spare) read a command, x16 devices (main area) 1 st page 2 nd page n th page block block area a area a/b area c (spare) read c command, x8/x16 devices 1 st page 2 nd page n th page block area a area a/b area c (spare) read c command, x8/x16 devices 1 st page 2 nd page n th page block 1 st page 2 nd page n th page block figure 13. sequential row read block diagrams busy busy busy tblbh1 (read busy time) tblbh1 tblbh1 address inputs i/o 00h/ 01h/50h 1st page output 2nd page output nth page output command code rb
rev 0.6 / oct. 2004 17 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash page program the page program operation is the standard operation to pr ogram data to the memory array. the main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. the max number of consecutive partial page program operations allowed in the same page is one in the main area and two in the spare area. after exceeding this a block erase command must be issued before any further program opera- tions can take place in that page. before starting a page program operation a pointer operat ion can be performed to poin t to the area to be pro- grammed. refer to the pointer operatio ns section and figure 9 for details. each page program operation consists of five steps (see figure 14): 1. one bus cycle is required to setup the page program command 2. four bus cycles are then required to input the program address (refer to table 3) 3. the data is then input (up to 528 bytes/ 264 words) and loaded into the page buffer 4. one bus cycle is required to is sue the confirm command to start th e program/ erase/read controller. 5. the program/ erase/read controller th en programs the data into the array. once the program operation has started the status register can be read using the read status register command. during program operations the status register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. during the program operation, only the read status regi ster and reset commands will be accepted, all other com- mands will be ignored. once the program operation has complete d the program/ erase/read controller bit sr6 is set to '1' and the ready/ busy signal goes high. the device remains in read status register mode until another valid command is written to the command interface. note: before starting a page program oper ation a pointer operation can be performed. refer to pointer section for details. figure 14. page program operation address inputs i/o 80h page program setup code data input 10h 70h sr0 confirm code read status register busy tblbh2 (program busy time) rb
rev 0.6 / oct. 2004 18 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash copy back program the copy back program operation is used to copy the data stored in one page and re program it in another page. the copy back program operation does no t require external memory and so the op eration is faster and more efficient because the reading and loading cycles are not required. the op eration is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. if the copy back program operation fails an error is signalle d in the status register. howe ver as the standard external ecc cannot be used with the copy back op eration bit error due to charge loss cannot be detected. for this reason it is recommended to limit the number of copy back operations on the same data and/or to improve the performance of the ecc. the copy back program operation requires three steps: - 1. the source page must be read using the read a co mmand (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). th is operation copies all 264 words/ 528 bytes from the page into the page buffer. - 2. when the device returns to the ready state (ready/busy high), the seco nd bus write cycle of the command is given with the 4 bus cycles to input the target page address. a25 must be the same for the source and target pages. - 3. then the confirm command is is sued to start the p/e/r controller. after a copy back program operation, a partial page program is not allowed in the target page until the block has been erased. see figure 15 for an example of the copy back operation. block erase erase operations are done one block at a time. an erase operat ion sets all of the bits in the addressed block to '1'. all previous data in the block is lost. an erase operat ion consists of three steps (refer to figure 17): 1. one bus cycle is required to setup the block erase command. 2. only three bus cycles for 512mb devices are required to input the block address. the first cycle (a0 to a7) is not required as only addresses a14 to a25 (highest address depends on device density) are valid, a9 to a13 are ignored. in the last address cycle i/o 0 to i/o 7 must be set to v il . 3. one bus cycle is required to issue the co nfirm command to start the p/e/r controller. figure 15. copy back operation source address inputs i/o 00h copy back code target address inputs 8ah 10h 70h read code read status register sr0 busy tblbh2 (program busy time) tblbh1 (read busy time) rb
rev 0.6 / oct. 2004 19 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash once the erase operation has completed the st atus register can be checked for errors. reset the reset command is used to reset the command interface and status register. if the reset command is issued dur- ing any operation, the operation will be aborted. if it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. if the device has already been reset then the new reset co mmand will not be accepted. the ready/busy signal goes low for t blbh4 after the reset command is issued. the value of t blbh4 depends on the operation that the device was performing when the command was issued, refer to table 15 for the values. read status register the device contains a status register which provides info rmation on the current or previous program or erase opera- tion. the various bits in the status register co nvey information and erro rs on the operation. the status register is read by issuing the read status re gister command. the status register information is present on the output data bus (i/o 0 - i/o 7 ) on the falling edge of chip enable or read enable, whichever occurs last. when several memories are connected in a system, the use of chip enable and read enable signal s allows the system to poll each device separately, even when the ready/busy pins ar e common-wired. it is not ne cessary to toggle the chip enable or read enable signals to update the contents of th e status register. after the read status register command has been issued, the device remains in read status register mode until another command is issued. therefore if a read status re gister command is issued during a random read cycle a new read command must be issued to continue with a page read or sequential row read operation. the status register bits are summarized in table 6, status register bits. refer to table 6 in conjunction with the fol- lowing text descriptions. write protection bit (sr7) the write protection bit can be used to identify if the device is protected or not. if the writ e protection bit is set to '1' the device is not protected and program or erase operations are allowed. if the write protection bit is set to '0' the device is protected and program or erase operations are not allowed. figure 17. block erase operation block address inputs i/o 60h confirm code d0h sr0 block erase setup code busy tblbh3 (erase busy time) rb 70h read status register
rev 0.6 / oct. 2004 20 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash p/e/r controller status register bit sr6 has two different f unctions depending on the current operation. during all other operations sr6 acts as a p/e/r controller bi t, which indicates whether the p/ e/r controller is active or inactive. when the p/e/r controller bit is set to '0', the p/e/ r controller is active (device is busy); when the bit is set to '1', the p/e/r controller is inactive (device is ready). p/e/r controller bit (sr5) the program/erase/read controller bit indicates whether the p/e/r controller is active or inactive. when the p/e/r controller bit is set to '0', the p/e/r controller is active (d evice is busy); when the bit is set to '1', the p/e/r controller is inactive (device is ready). error bit (sr0) the error bit is used to identify if any errors have been detected by the p/e/r controller. the error bit is set to '1' when a program or erase operation has failed to write the correct data to the memory. if the error bit is set to '0' the opera- tion has completed successfully. sr4, sr3 and sr2 are reserved
rev 0.6 / oct. 2004 21 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 6: status register bit read electronic signature the device contains a manufacturer code and device code. to read these codes two steps are required: 1. first use one bus write cycle to issue th e read electronic si gnature command (90h) 2. then subsequent bus read operations will read the manufacturer code and the device code until another command is issued. refer to table, read electronic signature for information on the addresses. automatic page 0 read at power-up automatic page 0 read at power-up is an option availabl e on all devices belonging to the nand flash 528 byte/264 word page family. it allows the microcontroller to directly download boot code from pa ge 0, without requiring any command or address input sequence. the automatic page 0 read option is particularly suited for applications that boot from the nand. devices delivered with automatic page 0 read at power-up can have the sequential row read option either enabled ordisabled. automatic page 0 re ad description. at powerup, once the supply voltage has reached the threshold level, v ccth , all digital outputs revert to their reset state and the internal nand device functions (reading, writing, erasing) are enabled. the device then automatically switches to read mode where, as in any read operation, the device is busy for a time t blbh1 during the data is transferred to the page buffer. once the data transfer is complete the ready/busy signal goes high. the data can then be read out se quentially on the i/o bus by pulsing th e read enable, re#, signal. figures 18 and 19 show the power-up waveforms for devices featuring the automatic page 0 read option. bit name logic level definition sr7 write protection '1' not protected '0' protected sr6 program/erase/read controller '1' p/e/r c inactive, device ready '0' p/e/r c active, device busy sr5 program/ erase/ read controller '1' p/e/r c inactive, device ready '0' p/e/r c active, device busy sr4, sr3, sr2 reserved don ' t care sr0 generic error '1' error - operation failed '0' no error - operation successful part number manufacture code device code bus width hy27us08121m adh 76h x8 HY27SS08121M adh 36h x8 hy27us16121m 00adh 0056h x16 hy27ss16121m 00adh 0046h x16
rev 0.6 / oct. 2004 22 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash sequential row read disabled if the device is delivered with sequential row read disabl ed and automatic read page 0 at power-up, only the first page (page 0) will be automatically read af ter the power-on sequence. refer to figure 18. sequential row read enabled if the device is delivered with the automatic page 0 read option only (sequential row read enabled), the device will automatically enter sequential row read mode after the power-up sequence, and start reading page 0, page 1, etc., until the last memory location is reached, each new page being accessed after a time t blbh1 . the sequential row read operation can be inhibi ted or interrupted by de-asserting e (set to v ih ) or by issuing a com- mand. refer to figure 19. note: (1). v ccth is equal to 2.5v for 3.3v po wer supply devices and to 1.5v for 1.8v power supply devices. data n+1 data n last data data n+2 tblbh1 busy vccth (1) vcc ale cle i/o re rb ce we data output from address n to last byte or word in page figure 18. sequential row read disabled and automatic page 0 read at power-up
rev 0.6 / oct. 2004 23 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash bad block management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block information is written prior to shipping. any block wh ere the 6th byte/ 1st word in the spare area of the 1st or 2nd page (if the 1st page is bad) does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in figure 20. block replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identi fied as attempts to program or erase th em will give errors in the status reg- ister. as the failure of a page program operation does not affect th e data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. the copy back program command can be us ed to copy the data to a valid block. see the ?copy back program? section for more details. refer to table 7 for the recommended procedure to follow if an error occurs during an operation. table 7: block failure operation recommended procedure erase block replacement program block replacement or ecc read ecc note: (1). v ccth is equal to 2.5v for 3.3v power supply devi ces and to 1.5v for 1.8v power supply devices. figure 19. automatic page 0 read at power-up (sequential row read enable) vccth(1) vcc we ce ale cle rb i/o tblbh1 (read busy time) busy busy busy busy tblbh1 tblbh1 tblbh1 page 0 data out page 1 data out page 2 data out page nth data out
rev 0.6 / oct. 2004 24 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 8: valid block program and erase times and endurance cycles the program and erase times and the number of prog ram/ erase cycles per block are shown in table 9. symbol para. min max unit n vb # of valid block 4016 4096 blocks figure 20. bad block management flowchart start block address= block 0 data =ffh? last block? end update bad block table increment block address yes no yes no
rev 0.6 / oct. 2004 25 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 9: program, erase time an d program erase endurance cycles maximum rating stressing the device above the ratings listed in table 10, absolute maximum ratings, may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indi- cated in the operating sections of this specification is no t implied. exposure to absolu te maximum rating conditions for extended periods may affect device reliability. table 10: absolution maximum rating note: (1). minimum voltage may undershoot to -2v for less than 20ns during transiti ons on input and i/o pins. maximum voltage may overshoot to v cc + 2v for less than 20ns during transitions on i/o pins. dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables th at follow, are derived from tests performed under the mea- surement conditions summarized in tabl e 11, operating and ac measurement cond itions. designers should check that the operating conditions in their circuit match the measur ement conditions when relyin g on the quoted parameters. parameters nand flash unit min typ max page program time 200 500 us block erase time 2 3 ms program/erase cycles (per block) 100,000 cycles data retention 10 years symbol parameter nand flash unit min max t bias temperature under bias -50 125 o c t stg storage temperature -65 150 o c v io (1) input or output voltage 1.8v devices -0.6 2.7 v 3.3 v devices -0.6 4.6 v v cc supply voltage 1.8v devices -0.6 2.7 v 3.3 v devices -0.6 4.6 v
rev 0.6 / oct. 2004 26 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 11: operating and ac measurement conditions note : (1). tbd table 12: capacitance note: t a = 25 o c , f = 1 mhz. c in and c i/o are not 100% tested. parameter nand flash unit min max supply voltage (v cc ) 1.8v devices 1.7 1.95 v 2.6v devices (1) 2.4 2.8 v 3.3v devices 2.7 3.6 v ambient temperature (t a ) commercial temp. 0 70 o c indurstrial temp. -40 85 o c load capacitance (c l ) (1 ttl gate and c l ) 1.8v devices 30 pf 2.6v devices (1) 30 pf 3.3v devices 100 pf input pulses voltages 1.8v devices 0 v cc v 2.6v devices (1) 0v cc v 3.3v devices 0.4 2.4 v input and output timing ref. voltages 1.8v devices v cc /2 v 2.6v devices (1) v 3.3v devices 1.5 v input rise and fall times 5 ns symbol parameter test condition typ max unit c in input capacitance v in = 0v 10 pf c i/o input/output capacitance v il = 0v 10 pf
rev 0.6 / oct. 2004 27 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 13: dc characteristics, 3.3v device and 1.8v device sym- bol parameter test condition 3.3v device 1.8v device unit min typ max min typ max i cc1 operating current sequentia read t rlrl minimum ce =v il , i out = 0 ma -10 20 - 8 15ma i cc2 program - - 10 20 - 8 15 ma i cc3 erase - - 10 20 - 8 15 ma i cc4 stand-by current (ttl) ce =v ih , wp =0v/v cc -- 1 - - 1ma i cc5 stand-by current (cmos) ce =v cc -0.2, wp =0/v cc - 10 50 - 10 50 ua i li input leakage current v in = 0 to v cc max - - 10 - - 10 ua i lo output leakage current v out = 0 to v cc max - - 10 - - 10 ua v ih input high voltage - 2.0 - v cc +0.3 v cc -0.4 v cc +0.3 v v il input low voltage - -0.3 - 0.8 -0.3 0.4 v v oh output high voltage level 3.3v i oh = -400ua 2.4 - - v cc -0.1 - - v 1.8v i oh = -100ua v ol output low voltage level 3.3v i ol = 2.1ma --0.4 - - 0.1v 1.8v i ol = 100ua i ol (rb ) output low current (rb ) 3.3v v ol = 0.4v 810 - 3 4 -ma 1.8v v ol = 0.1v v lko v dd supply voltage (erase and program lockout) - - - 2.5 - - 1.5 v
rev 0.6 / oct. 2004 28 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 14: ac characteristics for command, a ddress, data input (3.3v and 1.8v device) note: 1. if t elwl is less than 10ns, t wlwh must be minimum 35ns, otherwise, t wlwh may be minimum 25ns. symbol alt. symbol parameter 3.3v device 1.8v device unit t allwl t als address latch low to write enable low ale setup time min 0 ns t alhwl address latch hith to write enable low t clhwl t cls command latch high to write enable low cl setup time min 0 ns t cllwl command latch low to write enable low t dvwh t ds data valid to write enable high data setup time min 20 ns t elwl t cs chip enable low to write enable low ce setup time min 0 ns t whalh t alh write enable high to address latch high ale hold time min 10 ns t whall write enable high to address latch low t whclh t clh write enable high to command latch high cle hold time min 10 ns t whcll write enable high to command latch low t whdx t dh write enable high to data transition data hold time min 10 ns t wheh t ch write enable high to chip enable high ce hold time min 10 ns t whwh t wh write enable high to write enable low we high hold time min 15 20 ns t wlwh t wp write enable low to write enable high we pulse width min 25 (1) 60 ns t wlwl t wc write enable low to write enable low write cycle time min 50 80 ns
rev 0.6 / oct. 2004 29 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 15: ac characteristics for operation (3.3v device and 1.8v device) alt. sym- bol sym- bol parameter 3.3v device 1.8v device unit t allrl1 t ar1 address latch low to read enable low read electronic signature min 10 25 ns t allrl2 t ar2 read cycle min 50 80 ns t bhrl t rr ready/busy high to re ad enable low min 20 ns t blbh1 t r ready/busy low to ready/busy high read busy time, 512mb, 1gb 4) max 12 15 us t blbh2 t prog program busy time max 500 us t blbh3 t bers erase busy time max 3 ms t blbh4 t rst reset busy time, during ready max 5 us reset busy time, during read max 5 us reset busy time, during program max 10 us reset busy time, during erase max 500 us t cllrl t clr command latch low to read enable low min 10 ns t dzrl t ir data hi-z to read enable low min 0 ns t ehbh t cry chip enable high to ready/busy high (ce intercepted read) max 70+tr (1) ns t ehel t ceh chip enable high to chip enable low (2) min 100 ns t ehqz t chz chip enable high to output hi-z max 20 ns t elqv t cea chip enable low to output valid max 45 75 ns t rhbl t rb read enable high to ready/busy low max 100 ns t rhrl t reh read enable high to read enable low read enable high hold time min 15 20 ns t rhqz t rhz read enable high to output hi-z min 15 ns max 30 t rlrh t rp read enable low to read enable high read enable pulse width min 30 60 ns t rlrl t rc read enable low to read enable low read cycle time min 50 80 ns t rlqv t rea read enable low to output valid read enable access time max 35 60 ns t readid read es access time 45 t whbh t r write enable high to ready/busy high max 12 15 us t whbl t wb write enable high to ready/busy low max 100 ns
rev 0.6 / oct. 2004 30 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash note: (1). the time to ready depends on the value of the pull-u p resistor tied to the ready/busy pin. see figures 32, 33 and 34 . (2). to break the sequential read cycle, ce must be held high for longer than t ehel . (3). es = electronic signature. (4). 1g ddp t whrl t whr write enable high to read enable low min 60 ns t wlwl t wc write enable low to write enable low write cycle time min 50 80 ns alt. sym- bol sym- bol parameter 3.3v device 1.8v device unit figure 21. command latch ac waveforms command tclhwl (cle setup time) thwcll (cle hold time) telwl (ce setup time) twheh (ce hold time) twlwh tallwl (ale setup time) twhalh (ale hold time) tdvwh (data setup time) twhdx (data hold time) cle ale i/o ce we
rev 0.6 / oct. 2004 31 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 22. address latch ac waveforms figure 23. data input latch ac waveforms i/o we ce cle ale address cycle 1 address cycle 3 address cycle 2 address cycle 4 tcllwl (cle setup time) telwl (ce setup time) twlwl twlwl twlwl twlwh twlwh twlwh twlwh talhwl (ale setup time) twhwl twhwl twhwl twhall (ale hold time) twhall twhall tdvwh (data setup time) tdvwh tdvwh tdvwh twhdx (data hold time) twhdx twhdx twhdx i/o we ce data in 0 data in 1 data in last twhclh (cle hold time) twheh (ce hold time) twlwh twlwl tallwl (ale setup time) twlwh twlwh tdvwh (data setup time) tdvwh tdvwh twhdx (data hold time) twhdx twhdx cle ale
rev 0.6 / oct. 2004 32 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash note:1. cle = low, ale = low, we = high. figure 24. sequential data output after read ac waveforms figure 25. read status register ac waveform i/o re rb data out data out data out trlrl (read cycle time) tehqz trhqz trlqv trhqz trlqv tbhrl trhrl (re high holdtime) trlqv (re accesstime) ce i/o re ce we cle status register output 70h tcllrl twhcll twheh tclhwl telwl twlwh telqv twhrl tehqz trhqz trlqv tdzrl tdvwh (data setup time) twhdx (data hold time)
rev 0.6 / oct. 2004 33 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash note: refer to table(to see page 22) for the values of the manufacture and device codes. figure 26. read electronic signature ac waveform figure 27. read read a/ read b operation ac waveform i/o re ce man. code 90h device code don't care don't care 00h we ale cle read electronic signature command 1st cycle address manufacturer and device code reserved for future use tallrl1 trlqv (read es access time) i/o re ce we ale cle rb busy data output from address n to last byte or word in page data n add.n cycle 1 add.n cycle 2 add.n cycle 3 add.n cycle 4 00h or 01h data n+1 data n+2 data last address n input command code tehel twhwl twhbl twhbh tallrl2 trlrl (read cycle time) trhqz trhbl trlrh tblbh1 tehqz tehbh
rev 0.6 / oct. 2004 34 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash note: 1. a0-a7 is the address in the spare memory area, where a0-a3 are valid and a4-a7 are don't care . 2. only address cycle 4 is required. figure 28. read c operation, one page ac waveform i/o we ce cle ale re rb add. m cycle 1 50h data m add. m cycle 2 add. m cycle 3 add. m cycle 4 data last twhbh twhall tbhrl tallrl2 command code address m input busy data output from m to last byte or word in area c
rev 0.6 / oct. 2004 35 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 29. page program ac waveform i/o we ce cle ale re rb n last 10h 70h sr0 twlwl (write cycle time) twlwl twlwl twhbl tblbh2 (program busy time) address input data input confirm code page program read status register 80h add. n cycle 1 add. n cycle 2 add. n cycle 3 page program setup code
rev 0.6 / oct. 2004 36 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 30. block erase ac waveform figure 31. reset ac waveform i/o we ce cle ale re rb 70h sr0 60h add. n cycle 1 add. n cycle 2 add. n cycle 3 d0h tblbh3 (erase busy time) twlwl (write cycle time) block erase setup command block address input confirm code block erase read status register ffh tblbh4 (reset busy time) ale i/o re we cle rb
rev 0.6 / oct. 2004 37 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash system interface using ce don?t care to simplify system interface, ce may be deasserted during data loading or sequential data-reading as shown below. so, it is possible to connect nand flash to a microprocessor. the only function that was removed from standard nand flash to make ce don't care read operation was disabling of the automatic sequential read function. figure 32. program operation with ce don?t-care . figure 33. read operation with ce don?t-care. cle ale i/ox ce we ce don't-care tr 00h start add(4cycle) data output(sequential) re r/b if sequential row read enabled, ce must be held low during tr. cle ce don't-care ce we ale 80h start add(4cycle) data input data input 10h i/ox
rev 0.6 / oct. 2004 38 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash ready/busy signal electrical characteristics figures 32, 33 and 34 show the electrical characteristics for the ready/busy signal. the value required for the resistor r p can be calculated using the following equation: where i l is the sum of the input currents of all th e devices tied to the ready/busy signal. r p max is determined by the maximum value of tr. figure 34. ready/busy ac waveform figure 35. ready/busy load circuit ready v ol vcc v oh tr tf busy vcc device vss rp ibusy rb open drain output
rev 0.6 / oct. 2004 39 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash figure 36. resistor value wavefo rm timings for ready/busy signal 400 300 200 100 0 1234 1.7 1 2 3 4 1.7 1.7 1.7 1.7 30 60 90 120 0.85 0.57 0.43 vcc=1.8, cl=30pf rp(k ? ) tr, tf(ns) ibusy(ma) 400 300 200 100 0 1234 3.6 1 2 3 4 3.6 3.6 2.4 3.6 100 1.2 0.8 400 200 300 0.6 vcc=3.3, cl=100pf rp(k ? ) tr, tf(ns) ibusy(ma) tf ibus y t r
rev 0.6 / oct. 2004 40 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 16: 48-tsop1 - 48-lead plastic thin sma ll outline, 12 x 20mm, package mechanical data symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.050 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e0.500 l 0.500 0.680 alpha 0 5 figure 37. 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline
rev 0.6 / oct. 2004 41 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 17: 48-wsop1 - 48-lead plastic thin small outline, 12 x 17mm, package mechanical data symbol millimeters min typ max a 0.700 a1 0 0.080 a2 0.540 0.620 b 0.130 0.230 c 0.065 0.175 cp 0.050 d 11.910 12.000 12.120 d 16.900 17.000 17.100 e 15.300 15.400 15.500 e 0.500 l 0.450 0.750 alpha 0 figure 38. 48-wsop1 - 48-lead plastic very very thin small outline, 12 x 17mm, package outline
rev 0.6 / oct. 2004 42 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash table 17: 48-wsop1 - 48-lead plastic thin small outline, 12 x 17mm, package mechanical data symbol millimeters min typ max a 1.00 1.10 1.20 a1 0.21 0.26 0.31 a2 0.79 0.84 0.89 b 0.40 0.45 0.50 d 8.40 8.50 8.60 d1 4.00 d2 7.20 e 14.90 15.00 15.10 e1 5.60 e2 8.80 e0.80 fd 2.25 fd1 0.65 fe 4.70 fe1 3.10 sd 0.40 se 0.40 figure 39. 63-fbga - 8.5 x 15mm, 6x8 ball array 0.8mm pitch, pakage outline note: drawing is not to scale.
rev 0.6 / oct. 2004 43 hy27ss(08/16 )121m series hy27us(08/16 )121m series 512mbit (64mx8bit / 32 mx16bit) nand flash marking information package marking example tsop1 / wsop1 / fbga k o r h y 2 7 x s x x 1 2 1 m x x x x y w w x x - hynix - kor - hy27xsxx121mtxb hy: hynix 27: nand flash x: power supply s: classification xx: bit organization 12: density 1: mode m: version x: package type x: package material x: operating temperature x: bad block - y: year (ex: 4=year 2004, 05= year 2005) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - small letter : hynix symbol : origin country : u(2.7v~3.6v), s(1.7v~2.2v) : single level cell+single die : 08(x8), 16(x16) : 512mb : 1nce & 1r/nb; ce don't care : 1st generation : t(tsop1), v(wsop1), f(fbga) : blank(normal), p(lead free) : c(0 ~70 ), e(-25 ~85 ) i(-40 ~85 ) : b(included bad block), s(1~5 bad block), p(all good block) : fixed item : non-fixed item : part number

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